Index: src/arm_instructions.c
===================================================================
RCS file: /cvsroot/desmume/desmume/src/arm_instructions.c,v
retrieving revision 1.17
diff -r1.17 arm_instructions.c
28c28
< 
---
> #include "Disassembler.h"
237a238,239
> #define INDEX(i) ((((i)>>16)&0xFF0)|(((i)>>4)&0xF))
> 
241a244
> 	u32 a = cpu->instruct_adr;
243,245c246,270
< 	LOG("Undefined instruction: %08X\n", i);
< 	execute = FALSE;
< 	return 1;
---
> 
> 	/*
>         char txt[100];
>         des_arm_instructions_set[INDEX(i)](a, i, txt);
>         sprintf(txt, "%04X:%04X  %08X << %s >>",
> 		(int)((a&0x0FFFFFFF)>>16), (int)(a&0xFFFF), (int)i, txt);
> 	*/
> 	LOG("Undefined instruction: %#08X PC = %#08X\n", i, a);
> 
> 	if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9))){
> 		Status_Reg tmp = cpu->CPSR;
> 		armcpu_switchMode(cpu, UND);            /* enter und mode */
> 		cpu->R[14] = cpu->R[15] - 4;            /* jump to und Vector */
> 		cpu->SPSR = tmp;                        /* save old CPSR as new SPSR */
> 		cpu->CPSR.bits.T = 0;                   /* handle as ARM32 code */
> 		cpu->CPSR.bits.I = cpu->SPSR.bits.I;    /* keep int disable flag */
> 		cpu->R[15] = cpu->intVector + 0x04;
> 		cpu->next_instruction = cpu->R[15];
> 		return 4;
> 	}
> 	else
> 	{
> 		execute = FALSE;
> 		return 4;
> 	}
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<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7743,7746c7765
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7751,7754c7770
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7759,7762c7775
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7767,7770c7780
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7775,7778c7785
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7783,7786c7790
<      {
< 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7793,7796c7797
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7801,7804c7802
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7809,7812c7807
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7817,7820c7812
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7825,7828c7817
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7833,7836c7822
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7841,7844c7827
<      {
< 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
<           return 2;
<      }
---
> 	return OP_UND(cpu);
7919,7920c7902
<      execute = FALSE;
<      return 4;
---
> 	return OP_UND(cpu);